#include <asm/arch/common.h>
#include <asm/arch/sprd_reg.h>
#include "adi_hal_internal.h"

#define DCDC_CORE_VOSEL_DS_0P9V		0x120
#define DCDC_CORE_VOSEL_DS_0P8V		0x100
#define DCDC_CORE_VOSEL_DS_0P7V		0x0E0
#define DCDC_CORE_VOSEL_DS_0P65V	0x0D0
#define DCDC_CORE_VOSEL_DS_0P6V		0x0C0


void pmic_dcdc_ldo_config(void)
{
	ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x6e7f);
	while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );

	/*set LDOs & DCDCs PD or not*/
	//regulator_enable("vddcore");
	//regulator_enable("vddgen");
	//regulator_enable("vddwpa");
	//regulator_enable("avdd18");
	//regulator_enable("vddcamio");
	//regulator_enable("vddrf18a");
	//regulator_enable("vddrf18b");
	//regulator_enable("vddcamd");
	//regulator_enable("vddcon");
	//regulator_enable("ldomem");
	//regulator_disable("vddsim0");
	//regulator_disable("vddsim1");

	/*CP requires VDDSIM2 on in BOOT, demander:Jin.Song*/
	regulator_enable("vddsim2");

	//regulator_enable("vddcama");
	//regulator_enable("vddcammot");
	//regulator_enable("vddemmccore");
	//regulator_enable("vddsdcore");
	//regulator_enable("vddsdio");
	//regulator_enable("vdd28");
	//regulator_enable("vddwifipa");
	//regulator_enable("vdddcxo");
	//regulator_enable("vddusb33");

	ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);

	/*set xtl,io,ldo sleep enable in sleep mode*/
	ANA_REG_SET(ANA_REG_GLB_SLP_CTRL,
		BIT_LDO_XTL_EN |
		BIT_SLP_IO_EN |
		BIT_SLP_LDO_PD_EN |
		0
	);
	/*set dcdc power down in deep sleep mode*/
	ANA_REG_SET(ANA_REG_GLB_SLP_DCDC_PD_CTRL,
		BIT_SLP_DCDCCORE_DROP_EN|
		//BIT_SLP_DCDCWPA_PD_EN
		0
	);
	/*set ldo power down in deep sleep mode*/
	ANA_REG_SET(ANA_REG_GLB_SLP_LDO_PD_CTRL0,
		BIT_SLP_LDORF18A_PD_EN|
		//BIT_SLP_LDORF18B_PD_EN|
		//BIT_SLP_LDOEMMCCORE_PD_EN|
		//BIT_SLP_LDODCXO_PD_EN|
		//BIT_SLP_LDOWIFIPA_PD_EN|
		//BIT_SLP_LDOVDD28_PD_EN|
		//BIT_SLP_LDOSDCORE_PD_EN|
		//BIT_SLP_LDOSDIO_PD_EN|
		//BIT_SLP_LDOUSB33_PD_EN|
		//BIT_SLP_LDOCAMMOT_PD_EN|
		//BIT_SLP_LDOCAMIO_PD_EN|
		//BIT_SLP_LDOCAMD_PD_EN|
		//BIT_SLP_LDOCAMA_PD_EN|
		//BIT_SLP_LDOSIM2_PD_EN|
		//BIT_SLP_LDOSIM1_PD_EN |
		0
	);
	ANA_REG_SET(ANA_REG_GLB_SLP_LDO_PD_CTRL1,
		//BIT_SLP_LDOCP_PD_EN|
		//BIT_SLP_LDOCON_PD_EN|
		//BIT_SLP_LDOSIM0_PD_EN|
		BIT_SLP_LDOAVDD18_PD_EN|
		//BIT_SLP_LDOMEM_PD_EN|
		0
	);

	/*set dcdc lowpower mode enable in sleep mode*/
	ANA_REG_SET(ANA_REG_GLB_SLP_DCDC_LP_CTRL,
		BIT_SLP_DCDCCORE_LP_EN|
		BIT_SLP_DCDCGEN_LP_EN|
		BIT_SLP_DCDCWPA_LP_EN|
		0
	);

	/*set dcdccore drop voltage to 0.7V*/
	ANA_REG_OR(ANA_REG_GLB_DCDC_VLG_SEL, BIT_DCDC_CORE_SLP_SW_SEL);
	ANA_REG_SET(ANA_REG_GLB_DCDC_CORE_SLP_CTRL1,
		BITS_DCDC_CORE_VOSEL_DS_SW(DCDC_CORE_VOSEL_DS_0P7V)
		);

	/*set ldo lowpower mode enable in sleep mode*/
	ANA_REG_SET(ANA_REG_GLB_SLP_LDO_LP_CTRL0,
		BIT_SLP_LDORF18A_LP_EN|
		BIT_SLP_LDORF18B_LP_EN|
		BIT_SLP_LDOEMMCCORE_LP_EN|
		BIT_SLP_LDODCXO_LP_EN|
		BIT_SLP_LDOWIFIPA_LP_EN|
		BIT_SLP_LDOVDD28_LP_EN|
		BIT_SLP_LDOSDCORE_LP_EN|
		BIT_SLP_LDOSDIO_LP_EN|
		BIT_SLP_LDOUSB33_LP_EN|
		BIT_SLP_LDOCAMMOT_LP_EN|
		BIT_SLP_LDOCAMIO_LP_EN|
		BIT_SLP_LDOCAMD_LP_EN|
		BIT_SLP_LDOCAMA_LP_EN|
		BIT_SLP_LDOSIM2_LP_EN|
		BIT_SLP_LDOSIM1_LP_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_SLP_LDO_LP_CTRL1,
		BIT_SLP_LDOCON_LP_EN|
		BIT_SLP_LDOSIM0_LP_EN|
		BIT_SLP_LDOAVDD18_LP_EN|
		BIT_SLP_LDOMEM_LP_EN|
		0
	);

	/*set PAD control DCDC*/
	ANA_REG_SET(ANA_REG_GLB_DCDC_XTL_EN0,
		//BIT_DCDC_CORE_EXT_XTL0_EN|
		//BIT_DCDC_CORE_EXT_XTL1_EN|
		//BIT_DCDC_CORE_EXT_XTL2_EN|
		//BIT_DCDC_CORE_EXT_XTL3_EN|
		//BIT_DCDC_GEN_EXT_XTL0_EN|
		//BIT_DCDC_GEN_EXT_XTL1_EN|
		//BIT_DCDC_GEN_EXT_XTL2_EN|
		//BIT_DCDC_GEN_EXT_XTL3_EN|
		//BIT_DCDC_WPA_EXT_XTL0_EN|
		//BIT_DCDC_WPA_EXT_XTL1_EN|
		//BIT_DCDC_WPA_EXT_XTL2_EN|
		//BIT_DCDC_WPA_EXT_XTL3_EN|
		0
	);
	/*set PAD control LDO*/
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN0,
		//BIT_LDO_DCXO_EXT_XTL0_EN|
		//|BIT_LDO_DCXO_EXT_XTL1_EN
		//BIT_LDO_DCXO_EXT_XTL2_EN|
		//BIT_LDO_DCXO_EXT_XTL3_EN|
		//BIT_LDO_VDD28_EXT_XTL0_EN|
		//BIT_LDO_VDD28_EXT_XTL1_EN|
		//BIT_LDO_VDD28_EXT_XTL2_EN|
		//BIT_LDO_VDD28_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN1,
		//BIT_LDO_RF18A_EXT_XTL0_EN|
		//BIT_LDO_RF18A_EXT_XTL1_EN|
		//BIT_LDO_RF18A_EXT_XTL2_EN|
		//BIT_LDO_RF18A_EXT_XTL3_EN|
		//BIT_LDO_RF18B_EXT_XTL0_EN|
		//BIT_LDO_RF18B_EXT_XTL1_EN|
		//BIT_LDO_RF18B_EXT_XTL2_EN|
		//BIT_LDO_RF18B_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN2,
		//BIT_LDO_SIM0_EXT_XTL0_EN|
		//BIT_LDO_SIM0_EXT_XTL1_EN|
		//BIT_LDO_SIM0_EXT_XTL2_EN|
		//BIT_LDO_SIM0_EXT_XTL3_EN|
		//BIT_LDO_SIM1_EXT_XTL0_EN|
		//BIT_LDO_SIM1_EXT_XTL1_EN|
		//BIT_LDO_SIM1_EXT_XTL2_EN|
		//BIT_LDO_SIM1_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN3,
		//BIT_LDO_SIM2_EXT_XTL0_EN|
		//BIT_LDO_SIM2_EXT_XTL1_EN|
		//BIT_LDO_SIM2_EXT_XTL2_EN|
		//BIT_LDO_SIM2_EXT_XTL3_EN|
		//BIT_LDO_MEM_EXT_XTL0_EN|
		//BIT_LDO_MEM_EXT_XTL1_EN|
		//BIT_LDO_MEM_EXT_XTL2_EN|
		//BIT_LDO_MEM_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN4,
		//BIT_LDO_CAMMOT_EXT_XTL0_EN|
		//BIT_LDO_CAMMOT_EXT_XTL1_EN|
		//BIT_LDO_CAMMOT_EXT_XTL2_EN|
		//BIT_LDO_CAMMOT_EXT_XTL3_EN|
		//BIT_LDO_CAMIO_EXT_XTL0_EN|
		//BIT_LDO_CAMIO_EXT_XTL1_EN|
		//BIT_LDO_CAMIO_EXT_XTL2_EN|
		//BIT_LDO_CAMIO_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN5,
		//BIT_LDO_CAMA_EXT_XTL0_EN|
		//BIT_LDO_CAMA_EXT_XTL1_EN|
		//BIT_LDO_CAMA_EXT_XTL2_EN|
		//BIT_LDO_CAMA_EXT_XTL3_EN|
		//BIT_LDO_CAMD_EXT_XTL0_EN|
		//BIT_LDO_CAMD_EXT_XTL1_EN|
		//BIT_LDO_CAMD_EXT_XTL2_EN|
		//BIT_LDO_CAMD_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN6,
		//BIT_LDO_SDIO_EXT_XTL0_EN|
		//BIT_LDO_SDIO_EXT_XTL1_EN|
		//BIT_LDO_SDIO_EXT_XTL2_EN|
		//BIT_LDO_SDIO_EXT_XTL3_EN|
		//BIT_LDO_SDCORE_EXT_XTL0_EN|
		//BIT_LDO_SDCORE_EXT_XTL1_EN|
		//BIT_LDO_SDCORE_EXT_XTL2_EN|
		//BIT_LDO_SDCORE_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN7,
		//BIT_LDO_EMMCCORE_EXT_XTL0_EN|
		//BIT_LDO_EMMCCORE_EXT_XTL1_EN|
		//BIT_LDO_EMMCCORE_EXT_XTL2_EN|
		//BIT_LDO_EMMCCORE_EXT_XTL3_EN|
		//BIT_LDO_USB33_EXT_XTL0_EN|
		//BIT_LDO_USB33_EXT_XTL1_EN|
		//BIT_LDO_USB33_EXT_XTL2_EN|
		//BIT_LDO_USB33_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN8,
		//BIT_LDO_KPLED_EXT_XTL0_EN|
		//BIT_LDO_KPLED_EXT_XTL1_EN|
		//BIT_LDO_KPLED_EXT_XTL2_EN|
		//BIT_LDO_KPLED_EXT_XTL3_EN|
		//BIT_LDO_VIBR_EXT_XTL0_EN|
		//BIT_LDO_VIBR_EXT_XTL1_EN|
		//BIT_LDO_VIBR_EXT_XTL2_EN|
		//BIT_LDO_VIBR_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN9,
		//BIT_LDO_CON_EXT_XTL0_EN|
		//BIT_LDO_CON_EXT_XTL1_EN|
		//BIT_LDO_CON_EXT_XTL2_EN|
		//BIT_LDO_CON_EXT_XTL3_EN|
		//BIT_LDO_AVDD18_EXT_XTL0_EN|
		//BIT_LDO_AVDD18_EXT_XTL1_EN|
		//BIT_LDO_AVDD18_EXT_XTL2_EN|
		//BIT_LDO_AVDD18_EXT_XTL3_EN|
		0
	);
	ANA_REG_SET(ANA_REG_GLB_LDO_XTL_EN10,
		//BIT_LDO_CP_EXT_XTL0_EN|
		//BIT_LDO_CP_EXT_XTL1_EN|
		//BIT_LDO_CP_EXT_XTL2_EN|
		//BIT_LDO_CP_EXT_XTL3_EN|
		//BIT_LDO_WIFIPA_EXT_XTL0_EN|
		//BIT_LDO_WIFIPA_EXT_XTL1_EN|
		//BIT_LDO_WIFIPA_EXT_XTL2_EN|
		//BIT_LDO_WIFIPA_EXT_XTL3_EN|
		0
	);
}

void init_ldo_sleep_gr(void)
{
#ifdef CONFIG_FPGA
	return;
#endif
	pmic_dcdc_ldo_config();
	CSP_Init(0);
}
